Device Usage Page (usage_statistics_webtalk.html)

This HTML page displays the device usage statistics that will be sent to Xilinx.
To see the actual file transmitted to Xilinx, please click here.

software_version_and_target_device
betaFALSE build_version2348494
date_generatedTue Jan 15 05:03:48 2019 os_platformLIN64
product_versionVivado v2018.2.2 (64-bit) project_idec8d599ce404458eb44cd79beaf5f930
project_iteration12 random_id529b6bd35cbc550297ce4c62e9e6a3b8
registration_id529b6bd35cbc550297ce4c62e9e6a3b8 route_designTRUE
target_devicexc7z020 target_familyzynq
target_packageclg400 target_speed-1
tool_flowVivado

user_environment
cpu_nameIntel(R) Core(TM) i7-4870HQ CPU @ 2.50GHz cpu_speed2494.056 MHz
os_nameUbuntu os_releaseUbuntu 18.04.1 LTS
system_ram11.000 GB total_processors1

vivado_usage
gui_handlers
applyrsbmultiautomationdialog_checkbox_tree=5 basedialog_cancel=26 basedialog_ok=70 basedialog_yes=23
basereporttab_rerun=2 boardchooser_board_table=2 cmdmsgdialog_messages=2 cmdmsgdialog_ok=15
constraintschooserpanel_add_files=2 coretreetablepanel_core_tree_table=28 filesetpanel_file_set_panel_tree=37 flownavigatortreepanel_flow_navigator_tree=13
hacgccombobox_value_of_specified_parameter=2 hacgccombobox_value_of_specified_parameter_manual=2 hacgctextfield_value_of_specified_parameter=3 hacgctextfield_value_of_specified_parameter_manual=3
ipstatussectionpanel_upgrade_selected=6 mainmenumgr_checkpoint=2 mainmenumgr_export=4 mainmenumgr_file=14
mainmenumgr_flow=4 mainmenumgr_ip=3 mainmenumgr_open_recent_project=2 mainmenumgr_project=9
mainmenumgr_text_editor=3 mainmenumgr_tools=4 msgview_clear_messages_resulting_from_user_executed=2 newipwizard_create_new_axi4_ip_create_axi4=1
newipwizard_name_myip=1 pacommandnames_auto_update_hier=2 pacommandnames_create_top_hdl=13 pacommandnames_export_bd_tcl=3
pacommandnames_ip_packager_wizard=1 pacommandnames_new_project=1 pacommandnames_save_project_as=2 pacommandnames_save_rsb_design=4
pacommandnames_validate_rsb_design=16 pacommandnames_zoom_fit=3 pacommandnames_zoom_in=22 pacommandnames_zoom_out=21
planaheadtab_refresh_ip_catalog=2 projectnamechooser_project_name=3 rdicommands_custom_commands=1 rdicommands_delete=7
rsbapplyautomationbar_run_connection_automation=13 rsbblockproppanels_name=1 saveprojectutils_save=2 selectmenu_highlight=1
simpleoutputproductdialog_generate_output_products_immediately=6 simpleoutputproductdialog_synthesize_design_globally=1 srcmenu_refresh_hierarchy=2 systembuilderview_add_ip=13
systembuilderview_optimize_routing=3 systemtab_report_ip_status=2 systemtab_show_ip_status=5 xpg_tabbedpane_tabbed_pane=6
xpg_textfield_value_of_specified_parameter=4 xpg_textfield_value_of_specified_parameter_manual=6
java_command_handlers
createtophdl=13 customizersbblock=20 editdelete=7 editundo=1
exportrsbtclscript=3 ippackagerwizardhandler=1 newproject=1 reportipstatus=1
runbitgen=13 saveprojectas=2 saversbdesign=3 upgradeip=3
validatersbdesign=13 zoomfit=2 zoomin=20 zoomout=18
other_data
guimode=13
project_data
constraintsetcount=1 core_container=false currentimplrun=impl_1 currentsynthesisrun=synth_1
default_library=xil_defaultlib designmode=RTL export_simulation_activehdl=3 export_simulation_ies=3
export_simulation_modelsim=3 export_simulation_questa=3 export_simulation_riviera=3 export_simulation_vcs=3
export_simulation_xsim=3 implstrategy=Vivado Implementation Defaults launch_simulation_activehdl=0 launch_simulation_ies=0
launch_simulation_modelsim=0 launch_simulation_questa=0 launch_simulation_riviera=0 launch_simulation_vcs=0
launch_simulation_xsim=0 simulator_language=Mixed srcsetcount=2 synthesisstrategy=Vivado Synthesis Defaults
target_language=Verilog target_simulator=XSim totalimplruns=1 totalsynthesisruns=1

unisim_transformation
post_unisim_transformation
bibuf=130 bufg=1 carry4=518 dsp48e1=14
fdre=10989 fdse=279 gnd=1342 lut1=425
lut2=1216 lut3=2704 lut4=1118 lut5=774
lut6=1368 ps7=1 ramb18e1=7 ramb36e1=3
ramd32=1130 rams32=372 rams64e=32 srl16e=1260
srlc32e=236 vcc=542
pre_unisim_transformation
bibuf=130 bufg=1 carry4=518 dsp48e1=14
fdre=10989 fdse=279 gnd=1342 lut1=425
lut2=1216 lut3=2704 lut4=1118 lut5=774
lut6=1368 ps7=1 ram32m=186 ram32x1d=7
ram64x1s=32 ramb18e1=7 ramb36e1=3 srl16e=1260
srlc32e=236 vcc=542

power_opt_design
command_line_options_spo
-cell_types=default::all -clocks=default::[not_specified] -exclude_cells=default::[not_specified] -include_cells=default::[not_specified]
usage
bram_ports_augmented=9 bram_ports_newly_gated=2 bram_ports_total=20 flow_state=default
slice_registers_augmented=0 slice_registers_newly_gated=0 slice_registers_total=9939 srls_augmented=0
srls_newly_gated=0 srls_total=1455

ip_statistics
IP_Integrator/1
bdsource=SBD core_container=NA iptotal=1 maxhierdepth=1
numblks=35 numhdlrefblks=0 numhierblks=8 numhlsblks=0
numnonxlnxblks=0 numpkgbdblks=0 numreposblks=27 numsysgenblks=0
synth_mode=Global x_iplanguage=VERILOG x_iplibrary=BlockDiagram x_ipname=bd_afc3
x_ipvendor=xilinx.com x_ipversion=1.00.a
IP_Integrator/2
bdsource=USER core_container=NA da_axi4_cnt=3 da_clkrst_cnt=9
da_ps7_cnt=1 iptotal=1 maxhierdepth=0 numblks=13
numhdlrefblks=0 numhierblks=2 numhlsblks=0 numnonxlnxblks=2
numpkgbdblks=0 numreposblks=11 numsysgenblks=0 synth_mode=Global
x_iplanguage=VERILOG x_iplibrary=BlockDiagram x_ipname=design_1 x_ipvendor=xilinx.com
x_ipversion=1.00.a
axi_dma/1
c_dlytmr_resolution=125 c_enable_multi_channel=0 c_family=zynq c_include_mm2s=1
c_include_mm2s_dre=0 c_include_mm2s_sf=1 c_include_s2mm=1 c_include_s2mm_dre=0
c_include_s2mm_sf=1 c_include_sg=0 c_increase_throughput=0 c_m_axi_mm2s_addr_width=32
c_m_axi_mm2s_data_width=32 c_m_axi_s2mm_addr_width=32 c_m_axi_s2mm_data_width=32 c_m_axi_sg_addr_width=32
c_m_axi_sg_data_width=32 c_m_axis_mm2s_cntrl_tdata_width=32 c_m_axis_mm2s_tdata_width=32 c_micro_dma=0
c_mm2s_burst_size=16 c_num_mm2s_channels=1 c_num_s2mm_channels=1 c_prmry_is_aclk_async=0
c_s2mm_burst_size=16 c_s_axi_lite_addr_width=10 c_s_axi_lite_data_width=32 c_s_axis_s2mm_sts_tdata_width=32
c_s_axis_s2mm_tdata_width=32 c_sg_include_stscntrl_strm=0 c_sg_length_width=26 c_sg_use_stsapp_length=0
core_container=NA iptotal=1 x_ipcorerevision=18 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=axi_dma x_ipproduct=Vivado 2018.2.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=7.1
axi_protocol_converter_v2_1_17_axi_protocol_converter/1
c_axi_addr_width=32 c_axi_aruser_width=1 c_axi_awuser_width=1 c_axi_buser_width=1
c_axi_data_width=32 c_axi_id_width=12 c_axi_ruser_width=1 c_axi_supports_read=1
c_axi_supports_user_signals=0 c_axi_supports_write=1 c_axi_wuser_width=1 c_family=zynq
c_ignore_id=0 c_m_axi_protocol=2 c_s_axi_protocol=1 c_translation_mode=2
core_container=NA iptotal=1 x_ipcorerevision=17 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=axi_protocol_converter x_ipproduct=Vivado 2018.2.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=2.1
axis_data_fifo_v1_1_18_axis_data_fifo/1
c_aclken_conv_mode=0 c_axis_signal_set=0b00000000000000000000000000010111 c_axis_tdata_width=32 c_axis_tdest_width=1
c_axis_tid_width=1 c_axis_tuser_width=1 c_family=zynq c_fifo_depth=1024
c_fifo_mode=1 c_is_aclk_async=0 c_synchronizer_stage=2 core_container=NA
iptotal=1 x_ipcorerevision=18 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=axis_data_fifo x_ipproduct=Vivado 2018.2.2 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=1.1
bd_afc3/1
advanced_properties=0 component_name=design_1_axi_smc_0 core_container=NA has_aresetn=1
iptotal=1 num_clks=1 num_mi=1 num_si=2
x_ipcorerevision=9 x_iplanguage=VERILOG x_iplibrary=ip x_ipname=smartconnect
x_ipproduct=Vivado 2018.2.2 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.0
cordic_v6_0_14/1
c_architecture=2 c_coarse_rotate=0 c_cordic_function=6 c_data_format=2
c_has_aclk=1 c_has_aclken=0 c_has_aresetn=0 c_has_s_axis_cartesian=1
c_has_s_axis_cartesian_tlast=1 c_has_s_axis_cartesian_tuser=0 c_has_s_axis_phase=0 c_has_s_axis_phase_tlast=0
c_has_s_axis_phase_tuser=0 c_input_width=32 c_iterations=0 c_m_axis_dout_tdata_width=24
c_m_axis_dout_tuser_width=1 c_output_width=17 c_phase_format=0 c_pipeline_mode=-2
c_precision=0 c_round_mode=0 c_s_axis_cartesian_tdata_width=32 c_s_axis_cartesian_tuser_width=1
c_s_axis_phase_tdata_width=32 c_s_axis_phase_tuser_width=1 c_scale_comp=0 c_throttle_scheme=2
c_tlast_resolution=1 c_xdevicefamily=zynq core_container=false iptotal=1
x_ipcorerevision=14 x_iplanguage=VERILOG x_iplibrary=ip x_ipname=cordic
x_ipproduct=Vivado 2018.2.2 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=6.0
proc_sys_reset/1
c_aux_reset_high=0 c_aux_rst_width=4 c_ext_reset_high=0 c_ext_rst_width=4
c_family=zynq c_num_bus_rst=1 c_num_interconnect_aresetn=1 c_num_perp_aresetn=1
c_num_perp_rst=1 core_container=NA iptotal=1 x_ipcorerevision=12
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=proc_sys_reset x_ipproduct=Vivado 2018.2.2
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=5.0
processing_system7_v5.5_user_configuration/1
core_container=NA iptotal=1 pcw_apu_clk_ratio_enable=6:2:1 pcw_apu_peripheral_freqmhz=650
pcw_armpll_ctrl_fbdiv=26 pcw_can0_grp_clk_enable=0 pcw_can0_peripheral_clksrc=External pcw_can0_peripheral_enable=0
pcw_can0_peripheral_freqmhz=-1 pcw_can1_grp_clk_enable=0 pcw_can1_peripheral_clksrc=External pcw_can1_peripheral_enable=0
pcw_can1_peripheral_freqmhz=-1 pcw_can_peripheral_clksrc=IO PLL pcw_can_peripheral_freqmhz=100 pcw_cpu_cpu_pll_freqmhz=1300.000
pcw_cpu_peripheral_clksrc=ARM PLL pcw_crystal_peripheral_freqmhz=50 pcw_dci_peripheral_clksrc=DDR PLL pcw_dci_peripheral_freqmhz=10.159
pcw_ddr_ddr_pll_freqmhz=1050.000 pcw_ddr_hpr_to_critical_priority_level=15 pcw_ddr_hprlpr_queue_partition=HPR(0)/LPR(32) pcw_ddr_lpr_to_critical_priority_level=2
pcw_ddr_peripheral_clksrc=DDR PLL pcw_ddr_port0_hpr_enable=0 pcw_ddr_port1_hpr_enable=0 pcw_ddr_port2_hpr_enable=0
pcw_ddr_port3_hpr_enable=0 pcw_ddr_write_to_critical_priority_level=2 pcw_ddrpll_ctrl_fbdiv=21 pcw_enet0_enet0_io=MIO 16 .. 27
pcw_enet0_grp_mdio_enable=1 pcw_enet0_peripheral_clksrc=IO PLL pcw_enet0_peripheral_enable=1 pcw_enet0_peripheral_freqmhz=1000 Mbps
pcw_enet0_reset_enable=1 pcw_enet0_reset_io=MIO 9 pcw_enet1_grp_mdio_enable=0 pcw_enet1_peripheral_clksrc=IO PLL
pcw_enet1_peripheral_enable=0 pcw_enet1_peripheral_freqmhz=1000 Mbps pcw_enet1_reset_enable=0 pcw_enet_reset_polarity=Active Low
pcw_fclk0_peripheral_clksrc=IO PLL pcw_fclk1_peripheral_clksrc=IO PLL pcw_fclk2_peripheral_clksrc=IO PLL pcw_fclk3_peripheral_clksrc=IO PLL
pcw_fpga0_peripheral_freqmhz=100 pcw_fpga1_peripheral_freqmhz=50 pcw_fpga2_peripheral_freqmhz=50 pcw_fpga3_peripheral_freqmhz=50
pcw_fpga_fclk0_enable=1 pcw_fpga_fclk1_enable=0 pcw_fpga_fclk2_enable=0 pcw_fpga_fclk3_enable=0
pcw_gpio_emio_gpio_enable=0 pcw_gpio_mio_gpio_enable=1 pcw_gpio_mio_gpio_io=MIO pcw_gpio_peripheral_enable=0
pcw_i2c0_grp_int_enable=0 pcw_i2c0_peripheral_enable=0 pcw_i2c0_reset_enable=0 pcw_i2c1_grp_int_enable=0
pcw_i2c1_peripheral_enable=0 pcw_i2c1_reset_enable=0 pcw_i2c_reset_polarity=Active Low pcw_io_io_pll_freqmhz=1000.000
pcw_iopll_ctrl_fbdiv=20 pcw_irq_f2p_mode=DIRECT pcw_m_axi_gp0_freqmhz=10 pcw_m_axi_gp1_freqmhz=10
pcw_nand_cycles_t_ar=1 pcw_nand_cycles_t_clr=1 pcw_nand_cycles_t_rc=11 pcw_nand_cycles_t_rea=1
pcw_nand_cycles_t_rr=1 pcw_nand_cycles_t_wc=11 pcw_nand_cycles_t_wp=1 pcw_nand_grp_d8_enable=0
pcw_nand_peripheral_enable=0 pcw_nor_cs0_t_ceoe=1 pcw_nor_cs0_t_pc=1 pcw_nor_cs0_t_rc=11
pcw_nor_cs0_t_tr=1 pcw_nor_cs0_t_wc=11 pcw_nor_cs0_t_wp=1 pcw_nor_cs0_we_time=0
pcw_nor_cs1_t_ceoe=1 pcw_nor_cs1_t_pc=1 pcw_nor_cs1_t_rc=11 pcw_nor_cs1_t_tr=1
pcw_nor_cs1_t_wc=11 pcw_nor_cs1_t_wp=1 pcw_nor_cs1_we_time=0 pcw_nor_grp_a25_enable=0
pcw_nor_grp_cs0_enable=0 pcw_nor_grp_cs1_enable=0 pcw_nor_grp_sram_cs0_enable=0 pcw_nor_grp_sram_cs1_enable=0
pcw_nor_grp_sram_int_enable=0 pcw_nor_peripheral_enable=0 pcw_nor_sram_cs0_t_ceoe=1 pcw_nor_sram_cs0_t_pc=1
pcw_nor_sram_cs0_t_rc=11 pcw_nor_sram_cs0_t_tr=1 pcw_nor_sram_cs0_t_wc=11 pcw_nor_sram_cs0_t_wp=1
pcw_nor_sram_cs0_we_time=0 pcw_nor_sram_cs1_t_ceoe=1 pcw_nor_sram_cs1_t_pc=1 pcw_nor_sram_cs1_t_rc=11
pcw_nor_sram_cs1_t_tr=1 pcw_nor_sram_cs1_t_wc=11 pcw_nor_sram_cs1_t_wp=1 pcw_nor_sram_cs1_we_time=0
pcw_override_basic_clock=0 pcw_pcap_peripheral_clksrc=IO PLL pcw_pcap_peripheral_freqmhz=200 pcw_pjtag_peripheral_enable=0
pcw_preset_bank0_voltage=LVCMOS 3.3V pcw_preset_bank1_voltage=LVCMOS 1.8V pcw_qspi_grp_fbclk_enable=1 pcw_qspi_grp_fbclk_io=MIO 8
pcw_qspi_grp_io1_enable=0 pcw_qspi_grp_single_ss_enable=1 pcw_qspi_grp_single_ss_io=MIO 1 .. 6 pcw_qspi_grp_ss1_enable=0
pcw_qspi_internal_highaddress=0xFCFFFFFF pcw_qspi_peripheral_clksrc=IO PLL pcw_qspi_peripheral_enable=1 pcw_qspi_peripheral_freqmhz=200
pcw_qspi_qspi_io=MIO 1 .. 6 pcw_s_axi_acp_freqmhz=10 pcw_s_axi_gp0_freqmhz=10 pcw_s_axi_gp1_freqmhz=10
pcw_s_axi_hp0_data_width=64 pcw_s_axi_hp0_freqmhz=10 pcw_s_axi_hp1_data_width=64 pcw_s_axi_hp1_freqmhz=10
pcw_s_axi_hp2_data_width=64 pcw_s_axi_hp2_freqmhz=10 pcw_s_axi_hp3_data_width=64 pcw_s_axi_hp3_freqmhz=10
pcw_sd0_grp_cd_enable=1 pcw_sd0_grp_cd_io=MIO 47 pcw_sd0_grp_pow_enable=0 pcw_sd0_grp_wp_enable=0
pcw_sd0_peripheral_enable=1 pcw_sd0_sd0_io=MIO 40 .. 45 pcw_sd1_grp_cd_enable=0 pcw_sd1_grp_pow_enable=0
pcw_sd1_grp_wp_enable=0 pcw_sd1_peripheral_enable=0 pcw_sdio_peripheral_clksrc=IO PLL pcw_sdio_peripheral_freqmhz=50
pcw_single_qspi_data_mode=x4 pcw_smc_peripheral_clksrc=IO PLL pcw_smc_peripheral_freqmhz=100 pcw_spi0_grp_ss0_enable=0
pcw_spi0_grp_ss1_enable=0 pcw_spi0_grp_ss2_enable=0 pcw_spi0_peripheral_enable=0 pcw_spi1_grp_ss0_enable=0
pcw_spi1_grp_ss1_enable=0 pcw_spi1_grp_ss2_enable=0 pcw_spi1_peripheral_enable=0 pcw_spi_peripheral_clksrc=IO PLL
pcw_spi_peripheral_freqmhz=166.666666 pcw_tpiu_peripheral_clksrc=External pcw_tpiu_peripheral_freqmhz=200 pcw_trace_grp_16bit_enable=0
pcw_trace_grp_2bit_enable=0 pcw_trace_grp_32bit_enable=0 pcw_trace_grp_4bit_enable=0 pcw_trace_grp_8bit_enable=0
pcw_trace_peripheral_enable=0 pcw_ttc0_clk0_peripheral_clksrc=CPU_1X pcw_ttc0_clk0_peripheral_freqmhz=133.333333 pcw_ttc0_clk1_peripheral_clksrc=CPU_1X
pcw_ttc0_clk1_peripheral_freqmhz=133.333333 pcw_ttc0_clk2_peripheral_clksrc=CPU_1X pcw_ttc0_clk2_peripheral_freqmhz=133.333333 pcw_ttc0_peripheral_enable=0
pcw_ttc1_clk0_peripheral_clksrc=CPU_1X pcw_ttc1_clk0_peripheral_freqmhz=133.333333 pcw_ttc1_clk1_peripheral_clksrc=CPU_1X pcw_ttc1_clk1_peripheral_freqmhz=133.333333
pcw_ttc1_clk2_peripheral_clksrc=CPU_1X pcw_ttc1_clk2_peripheral_freqmhz=133.333333 pcw_ttc1_peripheral_enable=0 pcw_ttc_peripheral_freqmhz=50
pcw_uart0_baud_rate=115200 pcw_uart0_grp_full_enable=0 pcw_uart0_peripheral_enable=1 pcw_uart0_uart0_io=MIO 14 .. 15
pcw_uart1_baud_rate=115200 pcw_uart1_grp_full_enable=0 pcw_uart1_peripheral_enable=0 pcw_uart_peripheral_clksrc=IO PLL
pcw_uart_peripheral_freqmhz=100 pcw_uiparam_ddr_adv_enable=0 pcw_uiparam_ddr_al=0 pcw_uiparam_ddr_bank_addr_count=3
pcw_uiparam_ddr_bl=8 pcw_uiparam_ddr_board_delay0=0.279 pcw_uiparam_ddr_board_delay1=0.260 pcw_uiparam_ddr_board_delay2=0.085
pcw_uiparam_ddr_board_delay3=0.092 pcw_uiparam_ddr_bus_width=16 Bit pcw_uiparam_ddr_cl=7 pcw_uiparam_ddr_clock_0_length_mm=27.95
pcw_uiparam_ddr_clock_0_package_length=80.4535 pcw_uiparam_ddr_clock_0_propogation_delay=160 pcw_uiparam_ddr_clock_1_length_mm=27.95 pcw_uiparam_ddr_clock_1_package_length=80.4535
pcw_uiparam_ddr_clock_1_propogation_delay=160 pcw_uiparam_ddr_clock_2_length_mm=0 pcw_uiparam_ddr_clock_2_package_length=80.4535 pcw_uiparam_ddr_clock_2_propogation_delay=160
pcw_uiparam_ddr_clock_3_length_mm=0 pcw_uiparam_ddr_clock_3_package_length=80.4535 pcw_uiparam_ddr_clock_3_propogation_delay=160 pcw_uiparam_ddr_clock_stop_en=0
pcw_uiparam_ddr_col_addr_count=10 pcw_uiparam_ddr_cwl=6 pcw_uiparam_ddr_device_capacity=4096 MBits pcw_uiparam_ddr_dq_0_length_mm=32.2
pcw_uiparam_ddr_dq_0_package_length=98.503 pcw_uiparam_ddr_dq_0_propogation_delay=160 pcw_uiparam_ddr_dq_1_length_mm=31.08 pcw_uiparam_ddr_dq_1_package_length=68.5855
pcw_uiparam_ddr_dq_1_propogation_delay=160 pcw_uiparam_ddr_dq_2_length_mm=0 pcw_uiparam_ddr_dq_2_package_length=90.295 pcw_uiparam_ddr_dq_2_propogation_delay=160
pcw_uiparam_ddr_dq_3_length_mm=0 pcw_uiparam_ddr_dq_3_package_length=103.977 pcw_uiparam_ddr_dq_3_propogation_delay=160 pcw_uiparam_ddr_dqs_0_length_mm=32.14
pcw_uiparam_ddr_dqs_0_package_length=105.056 pcw_uiparam_ddr_dqs_0_propogation_delay=160 pcw_uiparam_ddr_dqs_1_length_mm=31.12 pcw_uiparam_ddr_dqs_1_package_length=66.904
pcw_uiparam_ddr_dqs_1_propogation_delay=160 pcw_uiparam_ddr_dqs_2_length_mm=0 pcw_uiparam_ddr_dqs_2_package_length=89.1715 pcw_uiparam_ddr_dqs_2_propogation_delay=160
pcw_uiparam_ddr_dqs_3_length_mm=0 pcw_uiparam_ddr_dqs_3_package_length=113.63 pcw_uiparam_ddr_dqs_3_propogation_delay=160 pcw_uiparam_ddr_dqs_to_clk_delay_0=-0.051
pcw_uiparam_ddr_dqs_to_clk_delay_1=-0.006 pcw_uiparam_ddr_dqs_to_clk_delay_2=-0.009 pcw_uiparam_ddr_dqs_to_clk_delay_3=-0.033 pcw_uiparam_ddr_dram_width=16 Bits
pcw_uiparam_ddr_ecc=Disabled pcw_uiparam_ddr_enable=1 pcw_uiparam_ddr_freq_mhz=525 pcw_uiparam_ddr_high_temp=Normal (0-85)
pcw_uiparam_ddr_memory_type=DDR 3 pcw_uiparam_ddr_partno=MT41J256M16 RE-125 pcw_uiparam_ddr_row_addr_count=15 pcw_uiparam_ddr_speed_bin=DDR3_1066F
pcw_uiparam_ddr_t_faw=40.0 pcw_uiparam_ddr_t_ras_min=35.0 pcw_uiparam_ddr_t_rc=48.91 pcw_uiparam_ddr_t_rcd=7
pcw_uiparam_ddr_t_rp=7 pcw_uiparam_ddr_train_data_eye=1 pcw_uiparam_ddr_train_read_gate=1 pcw_uiparam_ddr_train_write_level=1
pcw_uiparam_ddr_use_internal_vref=0 pcw_usb0_peripheral_enable=1 pcw_usb0_peripheral_freqmhz=60 pcw_usb0_reset_enable=1
pcw_usb0_reset_io=MIO 46 pcw_usb0_usb0_io=MIO 28 .. 39 pcw_usb1_peripheral_enable=0 pcw_usb1_peripheral_freqmhz=60
pcw_usb1_reset_enable=0 pcw_usb_reset_polarity=Active Low pcw_use_cross_trigger=0 pcw_use_m_axi_gp0=1
pcw_use_m_axi_gp1=0 pcw_use_s_axi_acp=0 pcw_use_s_axi_gp0=0 pcw_use_s_axi_gp1=0
pcw_use_s_axi_hp0=1 pcw_use_s_axi_hp1=0 pcw_use_s_axi_hp2=0 pcw_use_s_axi_hp3=0
pcw_wdt_peripheral_clksrc=CPU_1X pcw_wdt_peripheral_enable=0 pcw_wdt_peripheral_freqmhz=133.333333
processing_system7_v5_5_processing_system7/1
c_dm_width=4 c_dq_width=32 c_dqs_width=4 c_emio_gpio_width=64
c_en_emio_enet0=0 c_en_emio_enet1=0 c_en_emio_pjtag=0 c_en_emio_trace=0
c_fclk_clk0_buf=TRUE c_fclk_clk1_buf=FALSE c_fclk_clk2_buf=FALSE c_fclk_clk3_buf=FALSE
c_gp0_en_modifiable_txn=1 c_gp1_en_modifiable_txn=1 c_include_acp_trans_check=0 c_include_trace_buffer=0
c_irq_f2p_mode=DIRECT c_m_axi_gp0_enable_static_remap=0 c_m_axi_gp0_id_width=12 c_m_axi_gp0_thread_id_width=12
c_m_axi_gp1_enable_static_remap=0 c_m_axi_gp1_id_width=12 c_m_axi_gp1_thread_id_width=12 c_mio_primitive=54
c_num_f2p_intr_inputs=1 c_package_name=clg400 c_ps7_si_rev=PRODUCTION c_s_axi_acp_aruser_val=31
c_s_axi_acp_awuser_val=31 c_s_axi_acp_id_width=3 c_s_axi_gp0_id_width=6 c_s_axi_gp1_id_width=6
c_s_axi_hp0_data_width=64 c_s_axi_hp0_id_width=6 c_s_axi_hp1_data_width=64 c_s_axi_hp1_id_width=6
c_s_axi_hp2_data_width=64 c_s_axi_hp2_id_width=6 c_s_axi_hp3_data_width=64 c_s_axi_hp3_id_width=6
c_trace_buffer_clock_delay=12 c_trace_buffer_fifo_size=128 c_trace_internal_width=2 c_trace_pipeline_width=8
c_use_axi_nonsecure=0 c_use_default_acp_user_val=0 c_use_m_axi_gp0=1 c_use_m_axi_gp1=0
c_use_s_axi_acp=0 c_use_s_axi_gp0=0 c_use_s_axi_gp1=0 c_use_s_axi_hp0=1
c_use_s_axi_hp1=0 c_use_s_axi_hp2=0 c_use_s_axi_hp3=0 core_container=NA
iptotal=1 use_trace_data_edge_detector=0 x_ipcorerevision=6 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=processing_system7 x_ipproduct=Vivado 2018.2.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=5.5
sc_exit_v1_0_7_top/1
c_addr_width=32 c_enable_pipelining=0x1 c_family=zynq c_has_lock=0
c_is_cascaded=0 c_m_aruser_width=0 c_m_awuser_width=0 c_m_buser_width=0
c_m_id_width=0 c_m_limit_read_length=8 c_m_limit_write_length=8 c_m_protocol=1
c_m_ruser_bits_per_byte=0 c_m_ruser_width=0 c_m_wuser_bits_per_byte=0 c_m_wuser_width=0
c_max_ruser_bits_per_byte=0 c_max_wuser_bits_per_byte=0 c_mep_identifier_width=1 c_num_msc=1
c_rdata_width=64 c_read_acceptance=1 c_s_id_width=1 c_single_issuing=0
c_ssc_route_array=0b1001 c_ssc_route_width=2 c_wdata_width=64 c_write_acceptance=1
core_container=NA iptotal=1 x_ipcorerevision=7 x_iplanguage=VERILOG
x_iplibrary=ip x_ipname=sc_exit x_ipproduct=Vivado 2018.2.2 x_ipsimlanguage=MIXED
x_ipvendor=xilinx.com x_ipversion=1.0
sc_mmu_v1_0_6_top/1
c_addr_width=32 c_enable_pipelining=0x1 c_family=zynq c_id_width=0
c_is_cascaded=0 c_msc_route_array=0b1 c_msc_route_width=1 c_num_msc=1
c_num_seg=1 c_rdata_width=32 c_read_acceptance=32 c_s_aruser_width=0
c_s_awuser_width=0 c_s_buser_width=0 c_s_protocol=0 c_s_ruser_width=0
c_s_wuser_width=0 c_seg_base_addr_array=0x0000000000000000 c_seg_secure_read_array=0b0 c_seg_secure_write_array=0b0
c_seg_sep_route_array=0x0000000000000000 c_seg_size_array=0x0000001d c_seg_supports_read_array=0x1 c_seg_supports_write_array=0x1
c_single_issuing=0 c_supports_read_decerr=1 c_supports_wrap=1 c_supports_write_decerr=1
c_wdata_width=32 c_write_acceptance=32 core_container=NA iptotal=1
x_ipcorerevision=6 x_iplanguage=VERILOG x_iplibrary=ip x_ipname=sc_mmu
x_ipproduct=Vivado 2018.2.2 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.0
sc_mmu_v1_0_6_top/2
c_addr_width=32 c_enable_pipelining=0x1 c_family=zynq c_id_width=0
c_is_cascaded=0 c_msc_route_array=0b1 c_msc_route_width=1 c_num_msc=1
c_num_seg=1 c_rdata_width=32 c_read_acceptance=32 c_s_aruser_width=0
c_s_awuser_width=0 c_s_buser_width=0 c_s_protocol=0 c_s_ruser_width=0
c_s_wuser_width=0 c_seg_base_addr_array=0x0000000000000000 c_seg_secure_read_array=0b0 c_seg_secure_write_array=0b0
c_seg_sep_route_array=0x0000000000000000 c_seg_size_array=0x0000001d c_seg_supports_read_array=0x1 c_seg_supports_write_array=0x1
c_single_issuing=0 c_supports_read_decerr=1 c_supports_wrap=1 c_supports_write_decerr=1
c_wdata_width=32 c_write_acceptance=32 core_container=NA iptotal=1
x_ipcorerevision=6 x_iplanguage=VERILOG x_iplibrary=ip x_ipname=sc_mmu
x_ipproduct=Vivado 2018.2.2 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.0
sc_node_v1_0_9_top/10
c_aclk_relationship=1 c_aclken_conversion=0 c_addr_width=32 c_arbiter_mode=1
c_channel=1 c_disable_ip=0 c_enable_pipelining=0x01 c_family=zynq
c_fifo_ip=0 c_fifo_output_reg=1 c_fifo_size=5 c_fifo_type=0
c_id_width=1 c_m_num_bytes_array=0x00000008 c_m_pipeline=0 c_m_send_pipeline=1
c_max_payld_bytes=8 c_num_mi=1 c_num_si=1 c_payld_width=88
c_s_latency=0 c_s_num_bytes_array=0x00000004 c_s_pipeline=0 c_sc_route_width=1
c_synchronization_stages=3 c_user_bits_per_byte=0 c_user_width=512 core_container=NA
iptotal=1 x_ipcorerevision=9 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=sc_node x_ipproduct=Vivado 2018.2.2 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=1.0
sc_node_v1_0_9_top/1
c_aclk_relationship=1 c_aclken_conversion=0 c_addr_width=32 c_arbiter_mode=1
c_channel=2 c_disable_ip=0 c_enable_pipelining=0x01 c_family=zynq
c_fifo_ip=0 c_fifo_output_reg=1 c_fifo_size=5 c_fifo_type=0
c_id_width=1 c_m_num_bytes_array=0x00000008 c_m_pipeline=0 c_m_send_pipeline=0
c_max_payld_bytes=8 c_num_mi=1 c_num_si=2 c_payld_width=138
c_s_latency=1 c_s_num_bytes_array=0x0000000800000008 c_s_pipeline=0 c_sc_route_width=1
c_synchronization_stages=3 c_user_bits_per_byte=0 c_user_width=0 core_container=NA
iptotal=1 x_ipcorerevision=9 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=sc_node x_ipproduct=Vivado 2018.2.2 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=1.0
sc_node_v1_0_9_top/2
c_aclk_relationship=1 c_aclken_conversion=0 c_addr_width=32 c_arbiter_mode=1
c_channel=3 c_disable_ip=0 c_enable_pipelining=0x01 c_family=zynq
c_fifo_ip=0 c_fifo_output_reg=1 c_fifo_size=5 c_fifo_type=0
c_id_width=1 c_m_num_bytes_array=0x00000008 c_m_pipeline=0 c_m_send_pipeline=0
c_max_payld_bytes=8 c_num_mi=1 c_num_si=2 c_payld_width=138
c_s_latency=1 c_s_num_bytes_array=0x0000000800000008 c_s_pipeline=0 c_sc_route_width=1
c_synchronization_stages=3 c_user_bits_per_byte=0 c_user_width=0 core_container=NA
iptotal=1 x_ipcorerevision=9 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=sc_node x_ipproduct=Vivado 2018.2.2 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=1.0
sc_node_v1_0_9_top/3
c_aclk_relationship=1 c_aclken_conversion=0 c_addr_width=32 c_arbiter_mode=1
c_channel=4 c_disable_ip=0 c_enable_pipelining=0x01 c_family=zynq
c_fifo_ip=0 c_fifo_output_reg=1 c_fifo_size=5 c_fifo_type=0
c_id_width=1 c_m_num_bytes_array=0x0000000800000008 c_m_pipeline=0 c_m_send_pipeline=1
c_max_payld_bytes=8 c_num_mi=2 c_num_si=1 c_payld_width=6
c_s_latency=0 c_s_num_bytes_array=0x00000008 c_s_pipeline=0 c_sc_route_width=2
c_synchronization_stages=3 c_user_bits_per_byte=0 c_user_width=0 core_container=NA
iptotal=1 x_ipcorerevision=9 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=sc_node x_ipproduct=Vivado 2018.2.2 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=1.0
sc_node_v1_0_9_top/4
c_aclk_relationship=1 c_aclken_conversion=0 c_addr_width=32 c_arbiter_mode=1
c_channel=0 c_disable_ip=0 c_enable_pipelining=0x01 c_family=zynq
c_fifo_ip=0 c_fifo_output_reg=1 c_fifo_size=5 c_fifo_type=0
c_id_width=1 c_m_num_bytes_array=0x0000000800000008 c_m_pipeline=0 c_m_send_pipeline=1
c_max_payld_bytes=8 c_num_mi=2 c_num_si=1 c_payld_width=84
c_s_latency=0 c_s_num_bytes_array=0x00000008 c_s_pipeline=0 c_sc_route_width=2
c_synchronization_stages=3 c_user_bits_per_byte=0 c_user_width=0 core_container=NA
iptotal=1 x_ipcorerevision=9 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=sc_node x_ipproduct=Vivado 2018.2.2 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=1.0
sc_node_v1_0_9_top/5
c_aclk_relationship=1 c_aclken_conversion=0 c_addr_width=32 c_arbiter_mode=1
c_channel=1 c_disable_ip=0 c_enable_pipelining=0x01 c_family=zynq
c_fifo_ip=0 c_fifo_output_reg=1 c_fifo_size=5 c_fifo_type=0
c_id_width=1 c_m_num_bytes_array=0x00000008 c_m_pipeline=0 c_m_send_pipeline=0
c_max_payld_bytes=8 c_num_mi=1 c_num_si=2 c_payld_width=88
c_s_latency=1 c_s_num_bytes_array=0x0000000800000008 c_s_pipeline=0 c_sc_route_width=1
c_synchronization_stages=3 c_user_bits_per_byte=0 c_user_width=0 core_container=NA
iptotal=1 x_ipcorerevision=9 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=sc_node x_ipproduct=Vivado 2018.2.2 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=1.0
sc_node_v1_0_9_top/6
c_aclk_relationship=1 c_aclken_conversion=0 c_addr_width=32 c_arbiter_mode=1
c_channel=2 c_disable_ip=0 c_enable_pipelining=0x01 c_family=zynq
c_fifo_ip=0 c_fifo_output_reg=1 c_fifo_size=5 c_fifo_type=0
c_id_width=1 c_m_num_bytes_array=0x00000008 c_m_pipeline=0 c_m_send_pipeline=1
c_max_payld_bytes=8 c_num_mi=1 c_num_si=1 c_payld_width=138
c_s_latency=0 c_s_num_bytes_array=0x00000004 c_s_pipeline=0 c_sc_route_width=1
c_synchronization_stages=3 c_user_bits_per_byte=0 c_user_width=0 core_container=NA
iptotal=1 x_ipcorerevision=9 x_iplanguage=VERILOG x_iplibrary=ip
x_ipname=sc_node x_ipproduct=Vivado 2018.2.2 x_ipsimlanguage=MIXED x_ipvendor=xilinx.com
x_ipversion=1.0
sc_node_v1_0_9_top/7
c_aclk_relationship=1 c_aclken_conversion=0 c_addr_width=32 c_arbiter_mode=1
c_channel=3 c_disable_ip=0 c_enable_pipelining=0x01 c_family=zynq
c_fifo_ip=0 c_fifo_output_reg=1 c_fifo_size=5 c_fifo_type=0
c_id_width=1 c_m_num_bytes_array=0x00000008 c_m_pipeline=0 c_m_send_pipeline=1
c_max_payld_bytes=8 c_num_mi=1 c_num_si=1 c_payld_width=138
c_s_latency=0 c_s_num_bytes_array=0x00000004 c_s_pipeline=0 c_sc_route_width=1
c_synchronization_stages=3 c_user_bits_per_byte=0 c_user_width=0 core_container=NA
iptotal=1 x_ipcorerevision=9 x_iplanguage=VERILOG x_iplibrary=ip
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x_ipversion=1.0
sc_node_v1_0_9_top/8
c_aclk_relationship=1 c_aclken_conversion=0 c_addr_width=32 c_arbiter_mode=1
c_channel=4 c_disable_ip=0 c_enable_pipelining=0x01 c_family=zynq
c_fifo_ip=0 c_fifo_output_reg=1 c_fifo_size=5 c_fifo_type=0
c_id_width=1 c_m_num_bytes_array=0x0000000400000004 c_m_pipeline=0 c_m_send_pipeline=0
c_max_payld_bytes=8 c_num_mi=1 c_num_si=1 c_payld_width=6
c_s_latency=1 c_s_num_bytes_array=0x00000008 c_s_pipeline=0 c_sc_route_width=2
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iptotal=1 x_ipcorerevision=9 x_iplanguage=VERILOG x_iplibrary=ip
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x_ipversion=1.0
sc_node_v1_0_9_top/9
c_aclk_relationship=1 c_aclken_conversion=0 c_addr_width=32 c_arbiter_mode=1
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iptotal=1 x_ipcorerevision=9 x_iplanguage=VERILOG x_iplibrary=ip
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sc_si_converter_v1_0_6_top/1
c_addr_width=32 c_enable_pipelining=0x1 c_has_burst=0 c_id_width=1
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c_num_msc=1 c_num_read_threads=1 c_num_seg=1 c_num_write_threads=1
c_rdata_width=32 c_read_acceptance=32 c_read_watermark=0 c_s_ruser_bits_per_byte=0
c_s_wuser_bits_per_byte=0 c_sep_protocol_array=0x00000001 c_sep_rdata_width_array=0x00000040 c_sep_wdata_width_array=0x00000040
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c_write_watermark=0 core_container=NA iptotal=1 x_ipcorerevision=6
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=sc_si_converter x_ipproduct=Vivado 2018.2.2
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sc_si_converter_v1_0_6_top/2
c_addr_width=32 c_enable_pipelining=0x1 c_has_burst=0 c_id_width=1
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x_iplanguage=VERILOG x_iplibrary=ip x_ipname=sc_si_converter x_ipproduct=Vivado 2018.2.2
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sc_switchboard_v1_0_5_top/1
c_connectivity=11 c_m_pipelines=1 c_num_mi=1 c_num_si=2
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x_iplanguage=VERILOG x_iplibrary=ip x_ipname=sc_switchboard x_ipproduct=Vivado 2018.2.2
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sc_switchboard_v1_0_5_top/2
c_connectivity=11 c_m_pipelines=1 c_num_mi=1 c_num_si=2
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x_iplanguage=VERILOG x_iplibrary=ip x_ipname=sc_switchboard x_ipproduct=Vivado 2018.2.2
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sc_switchboard_v1_0_5_top/3
c_connectivity=0b11 c_m_pipelines=1 c_num_mi=2 c_num_si=1
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x_iplanguage=VERILOG x_iplibrary=ip x_ipname=sc_switchboard x_ipproduct=Vivado 2018.2.2
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=1.0
sc_switchboard_v1_0_5_top/4
c_connectivity=0b11 c_m_pipelines=1 c_num_mi=2 c_num_si=1
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x_iplanguage=VERILOG x_iplibrary=ip x_ipname=sc_switchboard x_ipproduct=Vivado 2018.2.2
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sc_switchboard_v1_0_5_top/5
c_connectivity=11 c_m_pipelines=1 c_num_mi=1 c_num_si=2
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xfft_v9_1_0/1
c_arch=3 c_bfly_type=0 c_bram_stages=3 c_channels=1
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c_has_nfft=0 c_has_ovflo=0 c_has_rounding=0 c_has_scaling=1
c_has_xk_index=0 c_input_width=16 c_m_axis_data_tdata_width=32 c_m_axis_data_tuser_width=1
c_m_axis_status_tdata_width=1 c_nfft_max=10 c_optimize_goal=0 c_output_width=16
c_reorder_mem_type=1 c_s_axis_config_tdata_width=16 c_s_axis_data_tdata_width=32 c_throttle_scheme=1
c_twiddle_mem_type=1 c_twiddle_width=16 c_use_flt_pt=0 c_use_hybrid_ram=0
c_xdevicefamily=zynq core_container=false iptotal=1 x_ipcorerevision=0
x_iplanguage=VERILOG x_iplibrary=ip x_ipname=xfft x_ipproduct=Vivado 2018.2.2
x_ipsimlanguage=MIXED x_ipvendor=xilinx.com x_ipversion=9.1
xpm_cdc_sync_rst/1
core_container=NA def_val=1'b1 dest_sync_ff=5 init=1
init_sync_ff=0 iptotal=1 sim_assert_chk=0 version=0
xpm_fifo_base/1
cdc_dest_sync_ff=2 common_clock=1 core_container=NA dout_reset_value=0
ecc_mode=0 en_adv_feature=16'b0001111100011111 en_ae=1'b1 en_af=1'b1
en_dvld=1'b1 en_of=1'b1 en_pe=1'b1 en_pf=1'b1
en_rdc=1'b1 en_uf=1'b1 en_wack=1'b1 en_wdc=1'b1
enable_ecc=0 fg_eq_asym_dout=1'b0 fifo_mem_type=0 fifo_memory_type=0
fifo_read_depth=16 fifo_read_latency=0 fifo_size=144 fifo_write_depth=16
full_reset_value=1 full_rst_val=1'b1 iptotal=3 pe_thresh_adj=8
pe_thresh_max=11 pe_thresh_min=5 pf_thresh_adj=8 pf_thresh_max=11
pf_thresh_min=5 prog_empty_thresh=10 prog_full_thresh=10 rd_data_count_width=4
rd_dc_width_ext=5 rd_latency=2 rd_mode=1 rd_pntr_width=4
read_data_width=9 read_mode=1 related_clocks=0 remove_wr_rd_prot_logic=0
sim_assert_chk=0 use_adv_features=1F1F version=0 wakeup_time=0
wr_data_count_width=5 wr_dc_width_ext=5 wr_pntr_width=4 wr_rd_ratio=0
write_data_width=9
xpm_memory_base/1
write_data_width=9 addr_width_a=5 addr_width_b=5 auto_sleep_time=0
byte_write_width_a=88 byte_write_width_b=88 clocking_mode=0 core_container=NA
ecc_mode=0 iptotal=17 max_num_char=0 memory_optimization=true
memory_primitive=1 memory_size=2816 memory_type=1 message_control=0
num_char_loc=0 p_ecc_mode=no_ecc p_enable_byte_write_a=0 p_enable_byte_write_b=0
p_max_depth_data=32 p_memory_opt=yes p_memory_primitive=distributed p_min_width_data=88
p_min_width_data_a=88 p_min_width_data_b=88 p_min_width_data_ecc=88 p_min_width_data_ldw=4
p_min_width_data_shft=88 p_num_cols_write_a=1 p_num_cols_write_b=1 p_num_rows_read_a=1
p_num_rows_read_b=1 p_num_rows_write_a=1 p_num_rows_write_b=1 p_sdp_write_mode=yes
p_width_addr_lsb_read_a=0 p_width_addr_lsb_read_b=0 p_width_addr_lsb_write_a=0 p_width_addr_lsb_write_b=0
p_width_addr_read_a=5 p_width_addr_read_b=5 p_width_addr_write_a=5 p_width_addr_write_b=5
p_width_col_write_a=88 p_width_col_write_b=88 read_data_width_a=88 read_data_width_b=88
read_latency_a=2 read_latency_b=1 read_reset_value_a=0 read_reset_value_b=0
use_embedded_constraint=0 use_mem_init=0 version=0 wakeup_time=0
write_data_width_a=88 write_data_width_b=88 write_mode_a=1 write_mode_b=1
xpm_memory_sdpram/1
write_mode_b=1 addr_width_a=5 addr_width_b=5 auto_sleep_time=0
byte_write_width_a=88 clocking_mode=0 core_container=NA ecc_mode=0
iptotal=14 memory_optimization=true memory_primitive=1 memory_size=2816
message_control=0 p_clocking_mode=0 p_ecc_mode=0 p_memory_optimization=1
p_memory_primitive=1 p_wakeup_time=0 p_write_mode_b=1 read_data_width_b=88
read_latency_b=1 read_reset_value_b=0 use_embedded_constraint=0 use_mem_init=0
wakeup_time=0 write_data_width_a=88 write_mode_b=1

report_drc
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -internal=default::[not_specified] -internal_only=default::[not_specified] -messages=default::[not_specified]
-name=default::[not_specified] -no_waivers=default::[not_specified] -return_string=default::[not_specified] -ruledecks=default::[not_specified]
-upgrade_cw=default::[not_specified] -waived=default::[not_specified]
results
dpip-1=4 reqp-165=3 reqp-181=2 rtstat-10=1

report_methodology
command_line_options
-append=default::[not_specified] -checks=default::[not_specified] -fail_on=default::[not_specified] -force=default::[not_specified]
-format=default::[not_specified] -messages=default::[not_specified] -name=default::[not_specified] -return_string=default::[not_specified]
-waived=default::[not_specified]
results
pdrc-190=1

report_power
command_line_options
-advisory=default::[not_specified] -append=default::[not_specified] -file=[specified] -format=default::text
-hier=default::power -l=default::[not_specified] -name=default::[not_specified] -no_propagation=default::[not_specified]
-return_string=default::[not_specified] -rpx=[specified] -verbose=default::[not_specified] -vid=default::[not_specified]
-xpe=default::[not_specified]
usage
airflow=250 (LFM) ambient_temp=25.0 (C) bi-dir_toggle=12.500000 bidir_output_enable=1.000000
board_layers=8to11 (8 to 11 Layers) board_selection=medium (10"x10") bram=0.008301 clocks=0.032628
confidence_level_clock_activity=High confidence_level_design_state=High confidence_level_device_models=High confidence_level_internal_activity=Medium
confidence_level_io_activity=High confidence_level_overall=Medium customer=TBD customer_class=TBD
devstatic=0.137121 die=xc7z020clg400-1 dsp=0.015628 dsp_output_toggle=12.500000
dynamic=1.355599 effective_thetaja=11.5 enable_probability=0.990000 family=zynq
ff_toggle=12.500000 flow_state=routed heatsink=none input_toggle=12.500000
junction_temp=42.2 (C) logic=0.018858 mgtavcc_dynamic_current=0.000000 mgtavcc_static_current=0.000000
mgtavcc_total_current=0.000000 mgtavcc_voltage=1.000000 mgtavtt_dynamic_current=0.000000 mgtavtt_static_current=0.000000
mgtavtt_total_current=0.000000 mgtavtt_voltage=1.200000 mgtvccaux_dynamic_current=0.000000 mgtvccaux_static_current=0.000000
mgtvccaux_total_current=0.000000 mgtvccaux_voltage=1.800000 netlist_net_matched=NA off-chip_power=0.000000
on-chip_power=1.492720 output_enable=1.000000 output_load=5.000000 output_toggle=12.500000
package=clg400 pct_clock_constrained=6.200000 pct_inputs_defined=0 platform=lin64
process=typical ps7=1.256323 ram_enable=50.000000 ram_write=50.000000
read_saif=False set/reset_probability=0.000000 signal_rate=False signals=0.023861
simulation_file=None speedgrade=-1 static_prob=False temp_grade=commercial
thetajb=7.4 (C/W) thetasa=0.0 (C/W) toggle_rate=False user_board_temp=25.0 (C)
user_effective_thetaja=11.5 user_junc_temp=42.2 (C) user_thetajb=7.4 (C/W) user_thetasa=0.0 (C/W)
vccadc_dynamic_current=0.000000 vccadc_static_current=0.020000 vccadc_total_current=0.020000 vccadc_voltage=1.800000
vccaux_dynamic_current=0.000000 vccaux_io_dynamic_current=0.000000 vccaux_io_static_current=0.000000 vccaux_io_total_current=0.000000
vccaux_io_voltage=1.800000 vccaux_static_current=0.014452 vccaux_total_current=0.014452 vccaux_voltage=1.800000
vccbram_dynamic_current=0.000397 vccbram_static_current=0.001203 vccbram_total_current=0.001600 vccbram_voltage=1.000000
vccint_dynamic_current=0.098879 vccint_static_current=0.013884 vccint_total_current=0.112763 vccint_voltage=1.000000
vcco12_dynamic_current=0.000000 vcco12_static_current=0.000000 vcco12_total_current=0.000000 vcco12_voltage=1.200000
vcco135_dynamic_current=0.000000 vcco135_static_current=0.000000 vcco135_total_current=0.000000 vcco135_voltage=1.350000
vcco15_dynamic_current=0.000000 vcco15_static_current=0.000000 vcco15_total_current=0.000000 vcco15_voltage=1.500000
vcco18_dynamic_current=0.000000 vcco18_static_current=0.000000 vcco18_total_current=0.000000 vcco18_voltage=1.800000
vcco25_dynamic_current=0.000000 vcco25_static_current=0.000000 vcco25_total_current=0.000000 vcco25_voltage=2.500000
vcco33_dynamic_current=0.000000 vcco33_static_current=0.000000 vcco33_total_current=0.000000 vcco33_voltage=3.300000
vcco_ddr_dynamic_current=0.351705 vcco_ddr_static_current=0.002000 vcco_ddr_total_current=0.353705 vcco_ddr_voltage=1.500000
vcco_mio0_dynamic_current=0.001750 vcco_mio0_static_current=0.001000 vcco_mio0_total_current=0.002750 vcco_mio0_voltage=3.300000
vcco_mio1_dynamic_current=0.002187 vcco_mio1_static_current=0.001000 vcco_mio1_total_current=0.003187 vcco_mio1_voltage=1.800000
vccpaux_dynamic_current=0.026155 vccpaux_static_current=0.010330 vccpaux_total_current=0.036485 vccpaux_voltage=1.800000
vccpint_dynamic_current=0.647225 vccpint_static_current=0.027927 vccpint_total_current=0.675152 vccpint_voltage=1.000000
vccpll_dynamic_current=0.013749 vccpll_static_current=0.003000 vccpll_total_current=0.016749 vccpll_voltage=1.800000
version=2018.2.2

report_utilization
clocking
bufgctrl_available=32 bufgctrl_fixed=0 bufgctrl_used=1 bufgctrl_util_percentage=3.13
bufhce_available=72 bufhce_fixed=0 bufhce_used=0 bufhce_util_percentage=0.00
bufio_available=16 bufio_fixed=0 bufio_used=0 bufio_util_percentage=0.00
bufmrce_available=8 bufmrce_fixed=0 bufmrce_used=0 bufmrce_util_percentage=0.00
bufr_available=16 bufr_fixed=0 bufr_used=0 bufr_util_percentage=0.00
mmcme2_adv_available=4 mmcme2_adv_fixed=0 mmcme2_adv_used=0 mmcme2_adv_util_percentage=0.00
plle2_adv_available=4 plle2_adv_fixed=0 plle2_adv_used=0 plle2_adv_util_percentage=0.00
dsp
dsp48e1_only_used=14 dsps_available=220 dsps_fixed=0 dsps_used=14
dsps_util_percentage=6.36
io_standard
blvds_25=0 diff_hstl_i=0 diff_hstl_i_18=0 diff_hstl_ii=0
diff_hstl_ii_18=0 diff_hsul_12=0 diff_mobile_ddr=0 diff_sstl135=0
diff_sstl135_r=0 diff_sstl15=1 diff_sstl15_r=0 diff_sstl18_i=0
diff_sstl18_ii=0 hstl_i=0 hstl_i_18=0 hstl_ii=0
hstl_ii_18=0 hsul_12=0 lvcmos12=0 lvcmos15=0
lvcmos18=1 lvcmos25=0 lvcmos33=1 lvds_25=0
lvttl=0 mini_lvds_25=0 mobile_ddr=0 pci33_3=0
ppds_25=0 rsds_25=0 sstl135=0 sstl135_r=0
sstl15=1 sstl15_r=0 sstl18_i=0 sstl18_ii=0
tmds_33=0
memory
block_ram_tile_available=140 block_ram_tile_fixed=0 block_ram_tile_used=6.5 block_ram_tile_util_percentage=4.64
ramb18_available=280 ramb18_fixed=0 ramb18_used=7 ramb18_util_percentage=2.50
ramb18e1_only_used=7 ramb36_fifo_available=140 ramb36_fifo_fixed=0 ramb36_fifo_used=3
ramb36_fifo_util_percentage=2.14 ramb36e1_only_used=3
primitives
bibuf_functional_category=IO bibuf_used=130 bufg_functional_category=Clock bufg_used=1
carry4_functional_category=CarryLogic carry4_used=490 dsp48e1_functional_category=Block Arithmetic dsp48e1_used=14
fdre_functional_category=Flop & Latch fdre_used=9680 fdse_functional_category=Flop & Latch fdse_used=259
lut1_functional_category=LUT lut1_used=214 lut2_functional_category=LUT lut2_used=1038
lut3_functional_category=LUT lut3_used=2738 lut4_functional_category=LUT lut4_used=1051
lut5_functional_category=LUT lut5_used=722 lut6_functional_category=LUT lut6_used=1021
ps7_functional_category=Specialized Resource ps7_used=1 ramb18e1_functional_category=Block Memory ramb18e1_used=7
ramb36e1_functional_category=Block Memory ramb36e1_used=3 ramd32_functional_category=Distributed Memory ramd32_used=614
rams32_functional_category=Distributed Memory rams32_used=204 rams64e_functional_category=Distributed Memory rams64e_used=32
srl16e_functional_category=Distributed Memory srl16e_used=1233 srlc32e_functional_category=Distributed Memory srlc32e_used=222
slice_logic
f7_muxes_available=26600 f7_muxes_fixed=0 f7_muxes_used=0 f7_muxes_util_percentage=0.00
f8_muxes_available=13300 f8_muxes_fixed=0 f8_muxes_used=0 f8_muxes_util_percentage=0.00
lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=442 lut_as_logic_available=53200 lut_as_logic_fixed=0
lut_as_logic_used=5363 lut_as_logic_util_percentage=10.08 lut_as_memory_available=17400 lut_as_memory_fixed=0
lut_as_memory_used=1341 lut_as_memory_util_percentage=7.71 lut_as_shift_register_fixed=0 lut_as_shift_register_used=899
register_as_flip_flop_available=106400 register_as_flip_flop_fixed=0 register_as_flip_flop_used=9939 register_as_flip_flop_util_percentage=9.34
register_as_latch_available=106400 register_as_latch_fixed=0 register_as_latch_used=0 register_as_latch_util_percentage=0.00
slice_luts_available=53200 slice_luts_fixed=0 slice_luts_used=6704 slice_luts_util_percentage=12.60
slice_registers_available=106400 slice_registers_fixed=0 slice_registers_used=9939 slice_registers_util_percentage=9.34
fully_used_lut_ff_pairs_fixed=9.34 fully_used_lut_ff_pairs_used=1726 lut_as_distributed_ram_fixed=0 lut_as_distributed_ram_used=442
lut_as_logic_available=53200 lut_as_logic_fixed=0 lut_as_logic_used=5363 lut_as_logic_util_percentage=10.08
lut_as_memory_available=17400 lut_as_memory_fixed=0 lut_as_memory_used=1341 lut_as_memory_util_percentage=7.71
lut_as_shift_register_fixed=0 lut_as_shift_register_used=899 lut_ff_pairs_with_one_unused_flip_flop_fixed=899 lut_ff_pairs_with_one_unused_flip_flop_used=2597
lut_ff_pairs_with_one_unused_lut_output_fixed=2597 lut_ff_pairs_with_one_unused_lut_output_used=2750 lut_flip_flop_pairs_available=53200 lut_flip_flop_pairs_fixed=0
lut_flip_flop_pairs_used=4807 lut_flip_flop_pairs_util_percentage=9.04 slice_available=13300 slice_fixed=0
slice_used=2746 slice_util_percentage=20.65 slicel_fixed=0 slicel_used=1789
slicem_fixed=0 slicem_used=957 unique_control_sets_used=280 using_o5_and_o6_fixed=280
using_o5_and_o6_used=556 using_o5_output_only_fixed=556 using_o5_output_only_used=31 using_o6_output_only_fixed=31
using_o6_output_only_used=312
specific_feature
bscane2_available=4 bscane2_fixed=0 bscane2_used=0 bscane2_util_percentage=0.00
capturee2_available=1 capturee2_fixed=0 capturee2_used=0 capturee2_util_percentage=0.00
dna_port_available=1 dna_port_fixed=0 dna_port_used=0 dna_port_util_percentage=0.00
efuse_usr_available=1 efuse_usr_fixed=0 efuse_usr_used=0 efuse_usr_util_percentage=0.00
frame_ecce2_available=1 frame_ecce2_fixed=0 frame_ecce2_used=0 frame_ecce2_util_percentage=0.00
icape2_available=2 icape2_fixed=0 icape2_used=0 icape2_util_percentage=0.00
startupe2_available=1 startupe2_fixed=0 startupe2_used=0 startupe2_util_percentage=0.00
xadc_available=1 xadc_fixed=0 xadc_used=0 xadc_util_percentage=0.00

router
usage
actual_expansions=6334697 bogomips=4988 bram18=7 bram36=3
bufg=0 bufr=0 congestion_level=0 ctrls=280
dsp=14 effort=2 estimated_expansions=9450810 ff=9939
global_clocks=1 high_fanout_nets=3 iob=0 lut=7166
movable_instances=21183 nets=31944 pins=125038 pll=0
router_runtime=0.000000 router_timing_driven=1 threads=3 timing_constraints_exist=1

synthesis
command_line_options
-assert=default::[not_specified] -bufg=default::12 -cascade_dsp=default::auto -constrset=default::[not_specified]
-control_set_opt_threshold=default::auto -directive=default::default -fanout_limit=default::10000 -flatten_hierarchy=default::rebuilt
-fsm_extraction=default::auto -gated_clock_conversion=default::off -generic=default::[not_specified] -include_dirs=default::[not_specified]
-keep_equivalent_registers=default::[not_specified] -max_bram=default::-1 -max_bram_cascade_height=default::-1 -max_dsp=default::-1
-max_uram=default::-1 -max_uram_cascade_height=default::-1 -mode=default::default -name=default::[not_specified]
-no_lc=default::[not_specified] -no_srlextract=default::[not_specified] -no_timing_driven=default::[not_specified] -part=xc7z020clg400-1
-resource_sharing=default::auto -retiming=default::[not_specified] -rtl=default::[not_specified] -rtl_skip_constraints=default::[not_specified]
-rtl_skip_ip=default::[not_specified] -seu_protect=default::none -sfcu=default::[not_specified] -shreg_min_size=default::3
-top=design_1_wrapper -verilog_define=default::[not_specified]
usage
elapsed=00:06:44s hls_ip=0 memory_gain=1274.020MB memory_peak=2576.070MB